This invention relates to phase-locked loop circuits and, more particularly, to phase-locked loop circuits which are especially, although not exclusively, suited for use in controllers for converting and formatting video data into digital data.
Phase-locked loop circuits are, of course, entirely conventional. Typical such circuits include a voltage controlled oscillator responsive to a control voltage for generating a periodic output signal comprised of pulses occurring at a first frequency determined by the value of the control voltage. A periodic feedback signal is then derived from the output signal and is compared with a reference signal to generate the requisite control voltage.
Controllers of the type above-described typically receive composite video data comprised of a video data component and a synchronization component including both horizontal sync pulses and vertical sync pulses. It is generally necessary to derive a sample clock signal from the horizontal sync pulses which has pulses at a frequency proportional to the horizontal sync pulses. A problem arises, however, since the horizontal sync pulses are normally missing during each vertical sync interval.
It would be desirable to provide a phase-locked loop circuit especially suited for use in a controller of the type above described that is capable of generating sample clock pulses which are stable in frequency and phase during each vertical sync interval notwithstanding the absence of horizontal sync pulses during that interval.